TTTC Header Image
TTTC's Electronic Broadcasting Service

Defect and Fault Tolerance in VLSI and Nanotechnology Systems IEEE Transactions on Emerging Topics in Computing
Special Issue/Section

CALL FOR PAPERS

Scope

The continuous scaling of CMOS devices as well as the increased interest in the use of emerging technologies make more and more important the topics related to defect and fault tolerance in VLSI and nanotechnology systems. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation, are of interest. 


The IEEE Transaction on Emerging Topics in Computing (TETC) seeks original manuscripts for a Special Section on Defect and Fault Tolerance in VLSI Systems scheduled to appear in the December issue of 2016. The topics of interest for this special issue include, but are not limited to:

  • Yield Analysis and Modeling: Defect/fault analysis and models; statistical yield modeling; critical area and metrics.
  • Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
  • Design For Testability in IC Design: FPGA, SoC, NoC, ASIC, microprocessors.
  • Error Detection, Correction, and Recovery: Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hardware/software techniques.
  • Dependability Analysis and Validation: Fault injection techniques and environments; dependability characterization.
  • Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing.
  • Defect and Fault Tolerance: Reliable circuit/system synthesis; radiation hardened and/or tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors; Performance, power, reliability tradeoffs.
  • Totally Fail-Safe Design for Critical Applications: Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
  • Emerging Technologies: Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
  • Hardware Security: Fault attacks, fault tolerance-based counter-measures, Scan-based attacks and countermeasures, hardware trojans, security versus reliability tradeoffs, interaction between VLSI test, trust, and reliability.

Other topics related to reliable and resilient computing.

Submitted articles must describe original research which is not published nor currently under review by other journals or conferences. Extended conference papers should contain at least 40% new material and will pass through the normal review process. As an author, you are responsible for understanding and adhering to our submission guidelines. You can access them at the IEEE Computer Society web site, www.computer.org. Please thoroughly read these before submitting your manuscript. TETC is the newest Transactions of the IEEE Computer Society with hybrid open access publishing model.

Submissions

Submitted articles must describe original research which is not published nor currently under review by other journals or conferences. Extended conference papers should contain at least 40% new material and will pass through the normal review process. As an author, you are responsible for understanding and adhering to our submission guidelines. You can access them at the IEEE Computer Society web site, www.computer.org. Please thoroughly read these before submitting your manuscript. TETC is the newest Transactions of the IEEE Computer Society with hybrid open access publishing model.

Please submit your paper to Manuscript Central at https://mc.manuscriptcentral.com/tetc-cs

Key Dates

  • Submission Deadline: December 1, 2015
  • Reviews Completed: March 1, 2016
  • Major Revisions Due (if Needed): April 1, 2016
  • Reviews of Revisions Completed (if Needed): May 1, 2016
  • Minor Revisions Due (if Needed): June 1, 2016
  • Notification of Final Acceptance: August 1, 2016
  • Publication Materials for Final Manuscripts Due: September 1, 2016 
  • Publication date: Last Issue of 2016 (Dec Issue)

Information

Please address all other correspondence regarding this special Section to the Guest Editors. 

Omer Khan (University of Connecticut) – khan@uconn.edu
Maria Michel (University of Cyprus) – mmichael@ucy.ac.cy
Salvatore Pontarelli (CNIT, IT) – salvatore.pontarelli@uniroma2.it



IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR
Michael Purtell
Intersil
- USA
Tel. +1-408-372-6015
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR

Synopsys, Inc.
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC
André IVANOV
U. of British Columbia - Canada
Tel. +1
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC 
Gumma University - Japan
Tel.+81-277-30-1111
E-mail k-hatayama@el.gunma-u.ac.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com


This message contains public information only. You are invited to copy and distribute it further.

For more information contact the TTTC office or visit http://tab.computer.org/tttc/

To remove or modify your contact information, or to register new users, please click here and follow the on-line instructions.